module clint_mod (
	rst,

	clint_int_i,
	
	external_int_o,
	clint_data_o
);

parameter int_count = 5;//1 gpio,2 uart_r,3 uart_t,4 uart_rf,5 uart_tf


input wire rst;
input wire [int_count-1:0] clint_int_i/* synthesis preserve */;
output reg external_int_o/* synthesis preserve */;
output reg [31:0] clint_data_o/* synthesis preserve */;

always @ (*) begin
	if ( rst == 1'b1 ) begin
		external_int_o <= 1'b0;
		clint_data_o <= 32'b0;
	end else begin
		external_int_o <= |clint_int_i;
		if ( clint_int_i[0] == 1'b1 ) begin
			clint_data_o <= 32'h21;
		end else if(clint_int_i[1] == 1'b1) begin
			clint_data_o <= 32'h22;
		end else if(clint_int_i[2] == 1'b1) begin
			clint_data_o <= 32'h23;
		end else if(clint_int_i[3] == 1'b1) begin
			clint_data_o <= 32'h24;
		end else if(clint_int_i[4] == 1'b1) begin
			clint_data_o <= 32'h25;
		end else begin
			clint_data_o <= 32'b0;
		end
	end
end	

endmodule
